Announcement: On-site Session Registration is Now Full
Thank you for your overwhelming support!
At this time, all on-site participation slots have reached full capacity.
We sincerely regret that we’re unable to accommodate further in-person registrations.
However, if you are highly interested in the event, please don’t hesitate to contact us — we’ll do our best to provide support or follow-up information.
For any questions or further details, please reach out to:
Taiwan Semiconductor Research Institute (TSRI)
I-Na Chen|ynchen@niar.org.tw
Li-An Yang|lianyang@niar.org.tw
Silicon Photonics and CPO at a Critical Moment
As next-generation data infrastructure evolves, the success of AI and HPC will increasingly hinge on breakthroughs in photonic-electronic integration. TSRI and its international partners are accelerating the development of a unified SiPh–CPO platform through silicon photonics, modular co-packaging, III-V and TFLN integration, high-speed test automation, and validation line support. Beyond technology, this forum launches an open ecosystem for technical specification co-definition, technical system-level validation, and academic–industry collaboration in education and talent development — empowering the next generation of engineers to shape the future of photonics-enabled computing.
TSRI–SiPhCPO Forum Highlights
CPO = Essential Packaging for SerDes-on-PIC Integration
Without the support of short-reach architectures and standardized design, it will be difficult to achieve large-scale deployment in data centers with performance targets such as energy consumption below 5 pJ/bit, data rates of 200–400 Gbps per lane, and overall throughput of 1.6–3.2 Tb/s.
TSRI’s Integrated Platform
8+ years of tape-out experience combined with a dedicated CPO validation line and full-stack 120 GHz/400G O/E testing flow.
III-V + Micro-Transfer Printing (MTP)
Laser, SOA, and TFLN modulators enabled via scalable MTP integration with high yield.
Electro-Opto-Thermal–3DIC Co-Design Flows
Advanced modeling frameworks to support CPO design convergence across packaging levels.
High-Performance Test & Spec Definition
Addressing integration tradeoffs in speed, loss, and reliability — toward holistic module + system verification.
Why attend the NIAR–TSRI SiPhCPO Forum?
The silicon photonics ecosystem is entering a critical phase, where system-driven design, high-speed testing, and heterogeneous integration must align for real-world deployment. This is the TSRI dedicated forum focused on Silicon Photonics Co-Packaged Optics (SiPh-CPO) and multi-party SIG collaboration, bringing together global experts, industry users, and academic leaders.
Whether you're looking to access advanced testing capabilities, validate chiplet modules, or join open platform development, this forum is your gateway to the next era of photonics–electronics integration.
Forum Venue
Forum Agenda and Speakers
Plenary Session
13:30–14:00 (07:30–08:00 CEST)|Opening
Learn MoreNIAR/TSRI & Prof. San-Liang Lee (NTUST)
14:00–14:25 (08:00–08:25 CEST)|iSiPP: a manufacturing platform for the next-gen Silicon Photonics
Learn MorePhilippe Absil (imec)
14:25–14:50 (08:25–08:50 CEST)|TSRI’s Role in Silicon Photonics and Co-Package Optics Platforms
Learn MoreMing-Wei Lin (TSRI)
14:50–15:20 (08:50–09:20 CEST)|Break
15:20–15:40 (09:20–09:40 CEST)|Hybrid III-V and TFLN integration on silicon photonics
Learn MoreProf. Gunther Roelkens (UGent)
15:40–16:00 (09:40–10:00 CEST)|Si Photonics applied to miniaturized mmWave-over-Fiber Antenna-in-Package
Learn MoreProf. Ming-Chang Lee (NTHU)
16:00–16:20 (10:00–10:20 CEST)|A 112Gb/s PAM-4 XSR Transceiver for CPO Application
Learn MoreProf. Pen-Jui Peng (NTHU)
16:20–16:35 (10:20–10:35 CEST)|Industry sharing (TBD)
16:35–16:45 (10:35–10:45 CEST)|Open Q&A Discussion